Lennart Van Hirtum recently graduated from KU Leuven with a Masters in Engineering Sciences, Computer Science, Artificial Intelligence. He is a performance-oriented developer, working mostly with C++, Java and he has a deep appreciation of low-level processor concerns. He also has an interest in hardware accelerators, so Verilog is no stranger to him either.

You can email me at lennart.vanhirtum@gmail.com
My GitHub